The present invention relates generally to testing integrated circuit devices and, more particularly, to very low voltage and bias scan testing methods.
Integrated circuit (IC) devices, such as microprocessors or system-on-chip (SOC) devices typically include a complex matrix of logic gates arranged to perform particular functions. These logic gates are often interconnected in two parallel arrangements, one arrangement for operation, and another arrangement for testing. Linking a plurality of flip flops together into a “scan chain” is one known method of arranging logic units for testing. Such a scan chain effectively forms a large shift register that can be used to gain access to internal nodes of the IC device in a test mode of operation. In such a test mode, typically the IC device is powered at its rated voltage level and in a first, scan shift phase, scan test patterns are shifted into scan chains at a pre-chosen clock rate. Then in a second phase, the IC device is put into a normal or ‘capture’ mode for one or more clock cycles. In a third phase, the IC device is placed in a scan shift mode again and the contents of the scan chain registers (which comprise the test results) are serially shifted out at the same clock rate for comparison with expected output values. This three phase test cycle is typically repeated many times.
It is known that certain manufacturing defects, such as interconnect bridging and gate-oxide shorts, are main causes of early life failures and reliability issues in IC devices. However, these defects often remain undetected by scan tests that are conducted at the normal voltage rating. It is also known that such defects do become evident during scan testing carried out at reduced power supply voltages.
The majority of logic circuits today operate at a power supply voltage of either 1.8 volts or 1.2 volts. However, correct logic operation can be sustained at a much lower voltage. In fact a logic circuit will function correctly, albeit at a reduced speed, as long as the output voltage of a logic gate is sufficient to switch the transistors in the driven gates. Hence, ‘very low voltage’ or VLV scan testing techniques have been developed that operate at relatively low values of supply voltages, typically at 0.8 volts for example. Normally, the clock rate is also reduced to take into account the longer propagation delays introduced by the use of a reduced supply voltage level. The known VLV scan testing method maintains a constant supply voltage level and a constant clock frequency throughout the scanning and capture phases. Although this method has the advantage of better detection of certain types of faults, a drawback is the reduced running speed of the test and therefore an extended overall test time. For example, a test that is run with reduced supply voltage can take ten times longer than one that is run at the rated voltage level. As product quality requirements increase, test costs become a greater contributor to the total device cost (typically up to 30%). It is desirable to reduce test cost while still keeping test quality at a high level.
Thus it would be advantageous to provide a way of reducing the overall test time of scan testing methods and of VLV scan tests in particular.